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k11p80m50sf4 k11 sub-family data sheet supports the following: mk11dx128vlk5, MK11DX256VLK5, mk11dn512vlk5 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 50 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb of program flash for devices without flexnvm. C up to 256 kb program flash for devices with flexnvm. C 64 kb flexnvm on flexmemory devices C 4 kb flexram on flexmemory devices C up to 64 kb ram C serial programming interface (ezport) ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C multiple low-power modes to provide power optimization based on application requirements C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C tamper detect and secure storage C hardware random-number generator C hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms C 128-bit unique identification (id) number per chip ? human-machine interface C general-purpose input/output ? analog modules C 16-bit sar adc C two analog comparators (cmp) containing a 6-bit dac and programmable reference input ? timers C programmable delay block C two 2-channel general purpose timers, one with quadrature decoder functionality C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C two spi modules C two i2c modules C four uart modules C i2s module freescale semiconductor document number: k11p80m50sf4 data sheet: advance information rev. 3, 08/2012 this document contains information on a new product. specifications and information herein are subject to change without notice. ? 2012C2013 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 5 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 6 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 7 3.8 definition: typical value..................................................... 7 3.9 typical value conditions .................................................... 8 4 ratings ...................................................................................... 9 4.1 thermal handling ratings ................................................... 9 4.2 moisture handling ratings .................................................. 9 4.3 esd handling ratings ......................................................... 9 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 10 5.1 ac electrical characteristics .............................................. 10 5.2 nonswitching electrical specifications ............................... 10 5.2.1 voltage and current operating requirements ......... 10 5.2.2 lvd and por operating requirements ................. 11 5.2.3 voltage and current operating behaviors .............. 12 5.2.4 power mode transition operating behaviors .......... 13 5.2.5 power consumption operating behaviors .............. 14 5.2.6 emc radiated emissions operating behaviors....... 17 5.2.7 designing with radiated emissions in mind ........... 18 5.2.8 capacitance attributes .......................................... 18 5.3 switching specifications..................................................... 18 5.3.1 device clock specifications ................................... 18 5.3.2 general switching specifications ........................... 19 5.4 thermal specifications ....................................................... 20 5.4.1 thermal operating requirements ........................... 20 5.4.2 thermal attributes ................................................. 20 6 peripheral operating requirements and behaviors .................... 21 6.1 core modules .................................................................... 21 6.1.1 jtag electricals .................................................... 21 6.2 system modules ................................................................ 24 6.3 clock modules ................................................................... 24 6.3.1 mcg specifications ............................................... 24 6.3.2 oscillator electrical specifications ......................... 26 6.3.3 32 khz oscillator electrical characteristics........... 28 6.4 memories and memory interfaces ..................................... 29 6.4.1 flash electrical specifications................................ 29 6.4.2 ezport switching specifications ............................ 32 6.5 security and integrity modules .......................................... 33 6.6 analog ............................................................................... 33 6.6.1 adc electrical specifications ................................. 33 6.6.2 cmp and 6-bit dac electrical specifications ......... 37 6.7 timers................................................................................ 40 6.8 communication interfaces ................................................. 40 6.8.1 dspi switching specifications (limited voltage range) .................................................................... 40 6.8.2 dspi switching specifications (full voltage range). 42 6.8.3 i2c switching specifications .................................. 44 6.8.4 uart switching specifications .............................. 44 6.8.5 normal run, wait and stop mode performance over the full operating voltage range ..................... 44 6.8.6 vlpr, vlpw, and vlps mode performance over the full operating voltage range ..................... 46 7 dimensions ............................................................................... 48 7.1 obtaining package dimensions ......................................... 48 8 pinout ........................................................................................ 48 8.1 k11 signal multiplexing and pin assignments .................. 48 8.2 k11 pinouts ....................................................................... 51 9 revision history ........................................................................ 52 k11 sub-family data sheet data sheet, rev. 3, 08/2012. 2 freescale semiconductor, inc.
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: pk11 and mk11 . 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status m = fully qualified, general market flow p = prequalification k## kinetis family k11 a key attribute d = cortex-m4 w/ dsp f = cortex-m4 w/ dsp and fpu m flash memory type n = program flash only x = program flash and flexmemory table continues on the next page... rdering parts 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc.
field description values fff program flash memory size 32 = 32 kb 64 = 64 kb 128 = 128 kb 256 = 256 kb 512 = 512 kb 1m0 = 1 mb r silicon revision z = initial (blank) = main a = revision after main t temperature range (?c) v = 40 to 105 c = 40 to 85 pp package identifier fm = 32 qfn (5 mm x 5 mm) ft = 48 qfn (7 mm x 7 mm) lf = 48 lqfp (7 mm x 7 mm) lh = 64 lqfp (10 mm x 10 mm) mp = 64 mapbga (5 mm x 5 mm) lk = 80 lqfp (12 mm x 12 mm) ll = 100 lqfp (14 mm x 14 mm) mc = 121 mapbga (8 mm x 8 mm) lq = 144 lqfp (20 mm x 20 mm) md = 144 mapbga (13 mm x 13 mm) mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) 5 = 50 mhz 7 = 72 mhz 10 = 100 mhz 12 = 120 mhz 15 = 150 mhz n packaging type r = tape and reel (blank) = trays 2.4 example this is an example part number: mk11dx128vlk5 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc
3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions ample his is an eample o an operating behavior hich is guaranteed i you meet the accompanying operating requirements ymbol escription in a nit igital o ea pullup pulldon current einition ttribute n attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements ample his is an eample o an attribute ymbol escription in a nit nput capacitance digital pins p erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc
3.4 definition: rating a rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating ymbol escription in a nit core supply voltage esult o eceeding a rating easured characteristic operating rating ailures in time ppm he lielihood o permanent chip ailure increases rapidly as soon as a characteristic begins to eceed one o its operating ratings erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc
3.6 relationship between ratings and operating requirements typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc
3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 ?c 105 ?c 25 ?c 40 ?c v dd (v) i (?a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 ?c v dd 3.3 v supply voltage 3.3 v terminology and guidelines k11 sub-family data sheet data sheet, rev. 3, 08/2012. 8 freescale semiconductor, inc.
4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature 55 150 ?c 1 t sdr solder temperature, lead-free 260 ?c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . .2 moisture handling ratings symbol description min. max. nit notes msl moisture sensitivity level 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . esd handling ratings symbol description min. max. nit notes hbm electrostatic discharge voltage, human body model -2000 2000 1 cdm electrostatic discharge voltage, charged-device model -500 500 2 i lat latch-up current at ambient temperature of 105c -100 100 ma 1. determined according to jedec standard jesd22-a11, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . oltage and current operating ratings symbol description min. max. nit dd digital supply voltage 0. . table continues on the next page... ratings 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc.
symbol description min. max. unit i dd digital supply current 155 ma v dio digital input voltage (except reset, extal, and xtal) 0.3 v v aio analog 1 , reset, extal, and xtal input voltage 0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all port pins) 25 25 ma v dda analog supply voltage v dd 0.3 v dd + 0.3 v v bat rtc battery supply voltage 0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications general k11 sub-family data sheet data sheet, rev. 3, 08/2012. 10 freescale semiconductor, inc.
5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd v dda v dd -to-v dda differential voltage 0.1 0.1 v v ss v ssa v ss -to-v ssa differential voltage 0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio i/o pin dc injection current single pin v in < v ss -0.3v (negative current injection) v in > v dd +0.3v (positive current injection) -3 +3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins negative current injection positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. 5.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v table continues on the next page... general 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 11
table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 ?s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength 2.7 v ? v dd ? 3.6 v, i oh = - 9 ma 1.71 v ? v dd ? 2.7 v, i oh = -3 ma v dd 0.5 v dd 0.5 v v output high voltage low drive strength 2.7 v ? v dd ? 3.6 v, i oh = -2 ma 1.71 v ? v dd ? 2.7 v, i oh = -0.6 ma v dd 0.5 v dd 0.5 v v i oht output high current total for all ports 100 ma table continues on the next page... general 11 sub-family data sheet data sheet, rev. , 0/2012. 12 freescale semiconductor, inc.
table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes v ol output low voltage high drive strength 2.7 v ? v dd ? 3.6 v, i ol = 9 ma 1.71 v ? v dd ? 2.7 v, i ol = 3 ma 0.5 0.5 v v output low voltage low drive strength 2.7 v ? v dd ? 3.6 v, i ol = 2 ma 1.71 v ? v dd ? 2.7 v, i ol = 0.6 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) @ full temperature range @ 25 ?c 1.0 0.1 ?a ?a 1 i oz hi-z (off-state) leakage current (per pin) 1 ?a i oz total hi-z (off-state) leakage current (all input pins) 4 ?a r pu internal pullup resistors 22 50 k? 2 r pd internal pulldown resistors 22 50 k? 3 1. tested by ganged leakage method 2. measured at vinput = v ss 3. measured at vinput = v dd 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsx table continues on the next page... general 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 1
table 5. power mode transition operating behaviors (continued) symbol description min. max. unit notes vlls3 table continues on the next page... general 11 sub-family data sheet data sheet, rev. , 0/2012. 1 freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ 40 to 25?c @ 50?c @ 70?c @ 105?c 2.19 4.35 8.92 35.33 3.4 ?a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ 40 to 25?c @ 50?c @ 70?c @ 105?c 1.77 2.81 5.20 19.88 3.1 ?a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ 40 to 25?c @ 50?c @ 70?c @ 105?c 1.03 1.92 4.03 17.43 1.8 ?a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled @ 40 to 25?c @ 50?c @ 70?c @ 105?c 543 na 1.36 3.39 16.52 1.1 ?a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled @ 40 to 25?c @ 50?c @ 70?c @ 105?c 359 na 1.03 2.87 15.20 950na ?a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v @ 40 to 25?c @ 50?c @ 70?c @ 105?c 0.91 1.1 1.5 4.3 1.1 1.35 1.85 5.7 ?a 9 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 50mhz core and system clock, 25mhz bus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 3. 50mhz core and system clock, 25mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, and peripherals are in active operation. 4. max values are measured with cpu executing dsp instructions 5. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flash clock. mcg configured for fei mode. 6. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. includes 32khz oscillator current and rtc operation. general k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 15
5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl figure 2. run mode supply current vs. core frequency general k11 sub-family data sheet data sheet, rev. 3, 08/2012. 16 freescale semiconductor, inc.
figure 3. vlpr mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors 1 symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.1550 19 db?v 2 , 3 v re2 radiated emissions voltage, band 2 50150 21 db?v v re3 radiated emissions voltage, band 3 150500 19 db?v v re4 radiated emissions voltage, band 4 5001000 11 db?v v re_iec iec level 0.151000 l 3 , 4 1. this data was collected on a mk20dn128vlh5 64pin lqfp device. 2. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each freuency range. general 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 1
3. v dd = 3.3 v, t a = 25 ?c, f osc = 12 mhz (crystal), f sys = 48 mhz, f bus = 48mhz 4. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 5.2. designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 5.2. capacitance attributes table . capacitance attributes symbol description min. max. nit c ina input capacitance: analog pins pf c ind input capacitance: digital pins pf 5. switching specifications 5..1 device clock specifications table . device clock specifications symbol description min. max. nit notes normal run mode f ss system and core clock 50 mhz f bs bus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz lpr mode 1 f ss system and core clock mhz f bs bus clock mhz f flash flash clock 1 mhz f ercl external reference clock 1 mhz f lptmrpin lptmr clock 25 mhz f lptmrercl lptmr external reference clock 1 mhz f i2smcl i2s master clock 12.5 mhz f i2sbcl i2s bit clock mhz general 11 sub-family data sheet data sheet, rev. , 0/2012. 1 freescale semiconductor, inc.
1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, cmt, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 13 7 36 24 ns ns ns ns 4 port rise and fall time (low drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 12 6 36 24 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75pf load 5. 15pf load general k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 19
5.4 thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature 40 125 ?c t a ambient temperature 40 105 ?c 5.4.2 thermal attributes board type symbol description 80 lqfp unit notes single-layer (1s) r
2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. for the lfp, the board meets the jesd51- specification. for the mapbga, the board meets the jesd51- specification. . determined according to jedec standard jesd51-, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. . determined according to jedec standard jesd51-, integrated circuit thermal test method environmental conditionsjunction-to-board . board temperature is measured on the top surface of the board near the package. 5. determined according to method 1012.1 of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. . determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . peripheral operating reuirements and behaviors .1 core modules .1.1 jtag electricals table 12. jtag limited voltage range electricals symbol description min. max. nit perating voltage 2. . j1 tcl freuency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 25 50 mhz j2 tcl cycle period 1/j1 ns j tcl clock pulse width boundary scan jtag and cjtag serial wire debug 50 20 10 ns ns ns j tcl rise and fall times ns j5 boundary scan input data setup time to tcl rise 20 ns j boundary scan input data hold time after tcl rise 0 ns j tcl low to boundary scan output data valid 25 ns j tcl low to boundary scan output high- 25 ns j tms, tdi input data setup time to tcl rise ns j10 tms, tdi input data hold time after tcl rise 1 ns j11 tcl low to td data valid 1 ns j12 tcl low to td high- 1 ns j1 trst assert time 100 ns j1 trst setup time (negation) to tcl high ns peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 21
table 13. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 4. test clock input timing peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 22 freescale semiconductor, inc.
j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 5. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 6. test access port timing peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 23
j14 j13 tclk trst figure 7. trst timing 6.2 system modules there are no specifications necessary for the devices system modules. 6.3 clock modules 6.3.1 mcg specifications table 14. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 ?c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. 2 freescale semiconductor, inc.
table 14. mcg specifications (continued) symbol description min. typ. max. unit notes fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2 , 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx32 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter f vco = 48 mhz f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 7 i pll pll operating current pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 7 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) f vco = 48 mhz f vco = 100 mhz 120 50 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) f vco = 48 mhz f vco = 100 mhz 1350 600 ps ps 8 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 25
table 14. mcg specifications (continued) symbol description min. typ. max. unit notes t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. 2 freescale semiconductor, inc.
table 15. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 25 400 500 2.5 3 4 ?a ?a ?a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 ?c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 27
6.3.2.2 oscillator frequency specifications table 16. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32 khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32 khz oscillator dc electrical specifications table 17. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m? c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 28 freescale semiconductor, inc.
6.3.3.2 32khz oscillator frequency specifications table 18. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 19. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 ?s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk256k erase block high-voltage time for 256 kb 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 29
6.4.1.2 flash timing specifications commands table 20. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk64k t rd1blk256k read 1s block execution time 64 kb program flash 256 kb program flash 0.9 1.7 ms ms t pgmchk program check execution time 45 ?s 1 t rdrsrc read resource execution time 30 ?s 1 t pgm4 program longword execution time 65 145 ?s t ersblk64k t ersblk256k erase flash block execution time 64 kb program flash 256 kb program flash 58 122 580 985 ms ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512 t pgmsec1k t pgmsec2k program section execution time 512 b flash 1 kb flash 2 kb flash 2.4 4.7 9.3 ms ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 ?s 1 t pgmonce program once execution time 65 ?s t ersall erase all blocks execution time 250 2000 ms 2 t vfykey verify backdoor access key execution time 30 ?s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time control code 0x01 control code 0x02 control code 0x04 control code 0x08 200 70 70 150 150 30 ?s ?s ?s ?s t pgmpart64k program partition for eeprom execution time 64 kb flexnvm 138 ms t setramff t setram32k t setram64k set flexram function execution time: control code 0xff 32 kb eeprom backup 64 kb eeprom backup 70 0.8 ?s ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 ?s 3 table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. 0 freescale semiconductor, inc.
table 20. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr8b32k t eewr8b64k t eewr8b128k byte-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 385 475 650 1800 2000 2400 ?s ?s ?s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 ?s t eewr16b32k t eewr16b64k t eewr16b128k word-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 385 475 650 1800 2000 2400 ?s ?s ?s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 ?s t eewr32b32k t eewr32b64k t eewr32b128k longword-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 630 810 1200 2050 2250 2675 ?s ?s ?s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash high voltage current behaviors table 21. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 22. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 1
table 22. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k write endurance eeprom backup to flexram ratio = 16 eeprom backup to flexram ratio = 128 eeprom backup to flexram ratio = 512 eeprom backup to flexram ratio = 4096 35 k 315 k 1.27 m 10 m 175 k 1.6 m 6.4 m 50 m writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25?c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40?c ? t j ? ?c. 3. write endurance represents the number of writes to each flexram location at -40?c ?tj ? ?c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.2 ezport switching specifications table 23. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 32 freescale semiconductor, inc.
ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 8. ezport timing diagram 6.5 security and integrity modules 6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 24 and table 25 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 24. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc.
table 24. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capacitance 16-bit mode 8-/10-/12-bit modes 8 4 10 5 pf r adin input resistance 2 5 k? r as analog source resistance 13-/12-bit modes f adck < 4 mhz 5 k? 3 f adck adc conversion clock frequency ? 13-bit mode 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate ? 13 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 ?c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance must be kept as low as possible to achieve the best results. the results in this data sheet were derived from a system which has < 8 ? analog source resistance. the r as /c as time constant should be kept to < 1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit must be set and the adlpc bit must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 34 freescale semiconductor, inc.
r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 5
table 25. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e q quantization error 16-bit modes ?13-bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode avg = 32 avg = 4 16-bit single-ended mode avg = 32 avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode avg = 32 16-bit single-ended mode avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.715 mv/?c v temp25 temp sensor voltage 25 ?c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit must be set, the hsc bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 36 freescale semiconductor, inc.
figure 10. typical enob vs. adc_clk for 16-bit differential mode figure 11. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 37
6.6.2 cmp and 6-bit dac electrical specifications table 26. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 ?a i ddls supply current, low-speed mode (en=1, pmode=0) 20 ?a v ain analog input voltage v ss 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 ?s i dac6b 6-bit dac current adder (enabled) 7 ?a inl 6-bit dac integral non-linearity 0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity 0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 38 freescale semiconductor, inc.
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 12. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 39
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 13. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.7 timers see general switching specifications . 6.8 communication interfaces peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 40 freescale semiconductor, inc.
6.8.1 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 27. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) 2 ns 1 ds dspisc to dspipcs n invalid delay (t bs x 2) 2 ns 2 ds5 dspisc to dspist valid .5 ns ds dspisc to dspist invalid 2 ns ds dspisin to dspisc input setup 15 ns ds dspisc to dspisin input hold 0 ns 1. the delay is programmable in spixctarnpssc and spixctarncssc. 2. the delay is programmable in spixctarnpasc and spixctarnasc. ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure 1. dspi classic spi timing master mode table 2. slave mode dspi timing (limited voltage range) num description min. max. nit perating voltage 2. . freuency of operation 12.5 mhz ds dspisc input cycle time x t bs ns table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc. 1
table 28. slave mode dspi timing (limited voltage range) (continued) num description min. max. unit ds10 dspi_sck input high/low time (t sck /2) 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 15. dspi classic spi timing slave mode 6.8.2 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 29. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) ns 2 table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. 2 freescale semiconductor, inc.
table 29. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds4 dspi_sck to dspi_pcs n invalid delay (t bs x 2) ns ds5 dspisc to dspist valid 10 ns ds dspisc to dspist invalid -.5 ns ds dspisin to dspisc input setup 20.5 ns ds dspisc to dspisin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum freuency of operation is reduced. 2. the delay is programmable in spixctarnpssc and spixctarncssc. . the delay is programmable in spixctarnpasc and spixctarnasc. ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure 1. dspi classic spi timing master mode table 0. slave mode dspi timing (full voltage range) num description min. max. nit perating voltage 1.1 . freuency of operation .25 mhz ds dspisc input cycle time x t bs ns ds10 dspisc input high/low time (t sc /2) - (t sc/2) ns ds11 dspisc to dspist valid 20 ns ds12 dspisc to dspist invalid 0 ns ds1 dspisin to dspisc input setup 2 ns ds1 dspisc to dspisin input hold ns ds15 dspiss active to dspist driven 1 ns ds1 dspiss inactive to dspist not driven 1 ns peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc.
first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 17. dspi classic spi timing slave mode 6.8.3 i 2 c switching specifications see general switching specifications . 6.8.4 uart switching specifications see general switching specifications . 6.8.5 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 31. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns table continues on the next page... peripheral operating reuirements and behaviors 11 sub-family data sheet data sheet, rev. , 0/2012. freescale semiconductor, inc.
table 31. i2s/sai master mode timing (continued) num. characteristic min. max. unit s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 25 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 18. i2s/sai timing master modes table 32. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 10 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 29 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 10 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 21 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 45
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 19. i2s/sai timing slave modes 6.8.6 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 33. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 75 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. 46 freescale semiconductor, inc.
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 20. i2s/sai timing master modes table 34. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 87 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 47
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 21. i2s/sai timing slave modes 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number: if you want the drawing for this package then use this document number 80-pin lqfp 98ass23174w 8 pinout 8.1 k11 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note ? the analog input signals adc0_se10, adc0_se11, adc0_dp1, and adc0_dm1 are available only for k11, dimensions k11 sub-family data sheet data sheet, rev. 3, 08/2012. 48 freescale semiconductor, inc.
k12, k21, and k22 devices and are not present on k10 and k20 devices. ? the trace signals on pte0, pte1, pte2, pte3, and pte4 are available only for k11, k12, k21, and k22 devices and are not present on k10 and k20 devices. ? if the vbat pin is not used, the vbat pin should be left floating. do not connect vbat pin to vss. ? the ftm_clkin signals on ptb16 and ptb17 are available only for k11, k12, k21, and k22 devices and are not present on k10 and k20 devices. for k11d devices this signal is on alt7, and for k11f devices, this signal is on alt4. ? ball a10, which is pte19 on k11d and k21d devices, is not available on k11f and k21f devices. 80 lqfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 adc0_se10 adc0_se10 pte0 spi1_pcs1 uart1_tx trace_clkout i2c1_sda rtc_clkout 2 adc0_se11 adc0_se11 pte1/ llwu_p0 spi1_sout uart1_rx trace_d3 i2c1_scl spi1_sin 3 adc0_dp1 adc0_dp1 pte2/ llwu_p1 spi1_sck uart1_cts_b trace_d2 4 adc0_dm1 adc0_dm1 pte3 spi1_sin uart1_rts_b trace_d1 spi1_sout 5 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx trace_d0 6 disabled pte5 spi1_pcs2 uart3_rx 7 vdd vdd 8 vss vss 9 adc0_se4a adc0_se4a pte16 spi0_pcs0 uart2_tx ftm_clkin0 ftm0_flt3 10 adc0_se5a adc0_se5a pte17 spi0_sck uart2_rx ftm_clkin1 lptmr0_alt3 11 adc0_se6a adc0_se6a pte18 spi0_sout uart2_cts_b i2c0_sda 12 adc0_se7a adc0_se7a pte19 spi0_sin uart2_rts_b i2c0_scl 13 adc0_dp0 adc0_dp0 14 adc0_dm0 adc0_dm0 15 adc0_dp3 adc0_dp3 16 adc0_dm3 adc0_dm3 17 vdda vdda 18 19 20 vssa vssa 21 tamper0/ rtc_wakeup_ b tamper0/ rtc_wakeup_ b 22 tamper1 tamper1 pinout k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 49
80 lqfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 23 xtal32 xtal32 24 extal32 extal32 25 vbat vbat 26 jtag_tclk/ swd_clk/ ezp_clk pta0 uart0_cts_b/ uart0_col_b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 27 jtag_tdi/ ezp_di pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 28 jtag_tdo/ trace_swo/ ezp_do pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do 29 jtag_tms/ swd_dio pta3 uart0_rts_b ftm0_ch0 jtag_tms/ swd_dio 30 nmi_b/ ezp_cs_b pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 31 disabled pta5 ftm0_ch2 i2s0_tx_bclk jtag_trst_b 32 disabled pta12 ftm1_ch0 i2s0_txd0 ftm1_qd_pha 33 disabled pta13/ llwu_p4 ftm1_ch1 i2s0_tx_fs ftm1_qd_phb 34 disabled pta14 spi0_pcs0 uart0_tx i2s0_rx_bclk i2s0_txd1 35 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 36 disabled pta16 spi0_sout uart0_cts_b/ uart0_col_b i2s0_rx_fs i2s0_rxd1 37 disabled pta17 spi0_sin uart0_rts_b i2s0_mclk 38 vdd vdd 39 vss vss 40 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 41 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_alt1 42 reset_b reset_b 43 adc0_se8 adc0_se8 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_pha 44 adc0_se9 adc0_se9 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_phb 45 adc0_se12 adc0_se12 ptb2 i2c0_scl uart0_rts_b ftm0_flt3 46 adc0_se13 adc0_se13 ptb3 i2c0_sda uart0_cts_b/ uart0_col_b ftm0_flt0 47 disabled ptb10 spi1_pcs0 uart3_rx ftm0_flt1 48 disabled ptb11 spi1_sck uart3_tx ftm0_flt2 49 disabled ptb12 uart3_rts_b ftm1_ch0 ftm0_ch4 ftm1_qd_pha 50 disabled ptb13 uart3_cts_b ftm1_ch1 ftm0_ch5 ftm1_qd_phb 51 disabled ptb16 spi1_sout uart0_rx ewm_in ftm_clkin0 52 disabled ptb17 spi1_sin uart0_tx ewm_out_b ftm_clkin1 53 disabled ptb18 ftm2_ch0 i2s0_tx_bclk ftm2_qd_pha 54 disabled ptb19 ftm2_ch1 i2s0_tx_fs ftm2_qd_phb 55 adc0_se14 adc0_se14 ptc0 spi0_pcs4 pdb0_extrg i2s0_txd1 pinout k11 sub-family data sheet data sheet, rev. 3, 08/2012. 50 freescale semiconductor, inc.
80 lqfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 56 adc0_se15 adc0_se15 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_b ftm0_ch0 i2s0_txd0 57 adc0_se4b/ cmp1_in0 adc0_se4b/ cmp1_in0 ptc2 spi0_pcs2 uart1_cts_b ftm0_ch1 i2s0_tx_fs 58 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 i2s0_tx_bclk 59 vss vss 60 vdd vdd 61 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out 62 disabled ptc5/ llwu_p9 spi0_sck lptmr0_alt2 i2s0_rxd0 cmp0_out ftm0_ch2 63 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_bclk i2s0_mclk 64 cmp0_in1 cmp0_in1 ptc7 spi0_sin i2s0_rx_fs 65 cmp0_in2 cmp0_in2 ptc8 i2s0_mclk 66 cmp0_in3 cmp0_in3 ptc9 i2s0_rx_bclk ftm2_flt0 67 disabled ptc10 i2c1_scl i2s0_rx_fs 68 disabled ptc11/ llwu_p11 i2c1_sda i2s0_rxd1 69 disabled ptc12 70 disabled ptc13 71 disabled ptc16 uart3_rx 72 disabled ptc17 uart3_tx 73 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_b 74 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_b 75 disabled ptd2/ llwu_p13 spi0_sout uart2_rx i2c0_scl 76 disabled ptd3 spi0_sin uart2_tx i2c0_sda 77 adc0_se21 adc0_se21 ptd4/ llwu_p14 spi0_pcs1 uart0_rts_b ftm0_ch4 ewm_in 78 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_b/ uart0_col_b ftm0_ch5 ewm_out_b 79 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 ftm0_flt0 80 adc0_se22 adc0_se22 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 8.2 k11 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 51
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vssa vrefl vrefh vdda adc0_dm3 adc0_dp3 adc0_dm0 adc0_dp0 pte19 pte18 pte17 pte16 vss vdd pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc17 ptc16 ptc13 ptc12 ptc11/llwu_p11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb19 ptb18 ptb17 ptb16 ptb13 ptb12 ptb11 ptb10 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 vbat extal32 xtal32 tamper1 tamper0/rtc_wakeup_b figure 22. k11 80 lqfp pinout diagram 9 revision history the following table provides a revision history for this document. revision history k11 sub-family data sheet data sheet, rev. 3, 08/2012. 52 freescale semiconductor, inc.
table 35. revision history rev. no. date substantial changes 1 6/2012 alpha customer release. 1.1 6/2012 in table 6, "power consumption operating behaviors", changed the units of i dd_vlls2 , i dd_vlls1 , i dd_vlls0 , and i dd_vbat from na to ?a. 2 7/2012 updated section "power consumption operating behaviors". updated section "flash timing specifications program and erase". updated section "flash timing specifications commands". removed the 32k ratio from "write endurance" in section "reliability specifications". updated iddstby maximum value in section "vreg electrical specifications". added the charts in section "diagram: typical idd_run operating behavior". 3 8/2012 updated section "power consumption operating behaviors". updated section "emc radiated emissions operating behaviors". updated section "mcg specifications". added applicable notes in section "signal multiplexing and pin assignments". revision history k11 sub-family data sheet data sheet, rev. 3, 08/2012. freescale semiconductor, inc. 53
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